library verilog;
use verilog.vl_types.all;
entity CLAmodule is
    port(
        Gb              : in     vl_logic_vector(3 downto 0);
        Pb              : in     vl_logic_vector(3 downto 0);
        CNb             : in     vl_logic;
        C               : out    vl_logic_vector(3 downto 0);
        X               : out    vl_logic;
        Y               : out    vl_logic;
        CN4b            : out    vl_logic
    );
end CLAmodule;
